Modern electronic systems that are implemented in application-specific integrated circuits (ASICs), field-programmable integrated circuits (FPGAs), or complex programmable logic devices (CPLDs) are often extremely complex, requiring years of effort to realize. For this reason, it is common to decompose the design problem into phases: a specification phase in which the functional requirements of the system are defined, a modeling phase in which an executable version of the functional description is realized, and an implementation phase in which a hardware realization of the system is created. For the end result to be correct, each phase must faithfully implement the result of the previous phase. For example, the hardware realization must exactly mirror the functional model created during the modeling phase. In practice, validating that implementations are faithful, which is the greatest part the design effort, often exposes design flaws or faulty assumptions upstream. This, in turn, results in reworking the earlier design representation.
The modeling phase consists of capturing the design in an executable form, simulating, then analyzing the results. The modeling phase is appropriate for algorithm exploration, in which system parameters such as sample rates, data precision, and choice of functional blocks are decided. This process is iterative, with the results of analysis leading to revisions that allow system specifications to be met. In the modeling phase, a high level of abstraction is desirable in order to facilitate algorithm exploration. For example, it is common to represent arithmetic values using floating point or fixed point rather than as buses of logic signals. Sampled data systems are also most conveniently modeled by defining sample rates rather than using explicit interconnections (“wires”) representing clock and associated control signals (e.g., enable, reset).
The hardware realization phase consists of creating a low-level implementation of the system in terms of primitives in an appropriate technology library. Hardware description languages such as VHDL and Verilog are commonly used for such a representation. In this representation, high level constructs such as sample rates and arithmetic values must be implemented in terms of clock signals and buses of logic vectors, and functional operators (e.g., discrete Fourier transform) must be mapped into appropriate circuitry. To achieve high performance, libraries of intellectual property (IP) blocks are commonly used. Such IP blocks are typically custom built to be efficient in the target technology.
In traditional system design flows, the system designer is responsible for creating both the system model and the hardware realization. Moreover, the designer must ensure that the hardware realization meets the system specification. This validation can be extremely time-consuming, especially if redesign of the system model is required.
For high-level modeling of digital signal processing (DSP) systems, a visual data flow paradigm has been found to be well suited and widely adopted by system architects. In a data flow model, the system is a network of functional operators that process data carried by signals between the operators. Since many DSP algorithms are naturally specified by signal flow graphs, the topology of a visual data flow model often closely resembles the algorithm specification. Specifying a system in a visual data flow environment is in some ways similar to specifying a design in a traditional schematic capture tool. Visual data flow environments provide a block editor, which can be used to construct models by connecting elements selected from libraries of functional blocks. In contrast to schematic tools, however, the library blocks and the simulation environment in a data flow tool provide a high level of functional abstraction, with polymorphic data types and operators to model arithmetic operations on integer, fixed-point, and floating-point data. Time evolution is typically specified by sample rates rather than by wiring explicit clocks.
Although previous design flow environments support system-level modeling, the costs associated with the high level of abstraction include inefficient hardware implementations and inexact modeling of the hardware in the system-level simulation. Prior existing visual data flow environments have been suitable for system modeling (i.e., specification and simulation), but have not provided automatic generation of a hardware realization of the system model. Instead, a typical design flow involves a manual translation of the system model to a hardware realization (e.g., ASIC or FPGA), and a manual verification that ensures the hardware faithfully implements the system model.
For example, the commercial visual data flow environment, SPW, from Cadence, provides simulation libraries and target implementations. However, the user is required to manually create the hardware implementation by explicitly replacing simulation models by the target library elements. This process is non-trivial, since replacement can involve one-to-many mapping (architectural synthesis, including re-timing and hardware sharing), as well as synthesis of additional circuitry for inferred control logic (handshaking and clocking).
A method and system that supports both modeling and automatic generation of a faithful and efficient hardware realization are therefore desirable.